On Sun, 26 Apr 2015 17:32:28 -0500, John Fields
wrote:

On Sun, 26 Apr 2015 09:32:28 -0400, rickman
wrote:

On 4/25/2015 6:03 PM, John Fields wrote:
On Sat, 25 Apr 2015 15:49:45 -0400, rickman
wrote:

On 4/23/2015 8:44 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:42:23 -0400, rickman
wrote:

On 4/19/2015 3:15 AM, John Fields wrote:
On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

I'm not sure what you are going on about. Jasen's circuit does visit
every value from 0 to 65535 and does not visit 65536. In fact, if you
set it to 65536 it remains locked in that state. I think your analysis
is faulty... or mine is. I coded it up in a spread sheet and don't see
any problems with it.

---
Code is often beguiling, hardware is not.

For a 16 bit PRSG, setting it to 65536 is the same as setting it to
all zeroes, and unless there's feedback provided to lift it out of
lockup, that's where it'll stay.

You seem to have run off into the weeds on this one.

---
Perhaps, but first of all, there's this:

DECIMAL BINARY
-------+---------------------
65535 1111 1111 1111 1111

So it should be apparent that it's impossible to set, or count to
decimal 65536 using a 16 bit register.

One extra count, to 65536, will result in the counter overflowing,
the MSB dropping into the bit bucket, and the counter's output
looking like this:

DECIMAL BINARY
-------+---------------------
65536 0000 0000 0000 0000

Get it?

Like I said, off in the weeds.

---
Nice dodge.

John Fields

There is no value-added by trying to educate the effete.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On 4/26/2015 6:29 PM, John Fields wrote:
On Sun, 26 Apr 2015 09:32:00 -0400, rickman
wrote:

On 4/25/2015 5:23 PM, John Fields wrote:
On Sat, 25 Apr 2015 15:49:06 -0400, rickman
wrote:

On 4/23/2015 8:06 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:35:38 -0400, rickman
wrote:

On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman
wrote:

On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman
wrote:

On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman
wrote:

On 4/16/2015 4:46 PM, John Fields wrote:

If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields


I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.

---
What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.

Can you post a contradictory example culled from the "larger field
of contenders" ?

I don't see where you have provided any examples to contradict.

---
I already posted a link to an 8 bit PRSG with 256 output states.

Did you miss it?

Apparently.

---
Well, then, for your perusal, here ya go:

https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0

This is hardly a "huge" counter...

---
Indeed, but the point made was to illustrate that NORing the outputs
of all of the stages preceding the rightmost and using that feedback
to force the PRSG into and out of the lockup state would cause it to
visit all of the 2^n possible states for that length of PRSG.

Uh, I had already indicated that this was possible and posted a link to
Peter Alfkie's app note about this for small LFSRs. So you are
restating my point.

---
As I recall, the schematic your link pointed to was a little
confusing - to me, anyway - so I decided to post something better
organized in order to illustrate the concept more clearly, not to
mention a working simulation. Which, BTW, neither you nor Alfkie
presented.

In any case, just for your information, that circuit's been around
since at least the late '60s, when I first came across it being used
as a bias-free scrambler.
---




Faulting the example because the counter isn't huge is disingenuous
since, if the lockup state is needed as part of the pattern, all
that's really needed to scale up to any PRSG length is a bunch of
diodes, a pullup resistor to Vcc, and an inverter on the outputs of
the diodes.

A bunch of diodes? I guess so, but the speed issue still remains.

---
How so?

if the diodes are all commoned on one end and followed by an
inverter, then the worst case delay will be one gate plus one diode,
which should be less than the delay through a stage of shift and
then back to the input through an EXOR.

The speed of your breadboard circuit is not really relevant. The speed
of a VLSI ASIC or an FPGA is what 99.999% of people will care about.
There is a reason why DTL is no longer used. Besides, the circuit slows
down with every diode added.

---
If you go back to the beginning, you'll see that my offering was in
reference to Jim's request for a circuit which was to be simulated
in 74XX, so that's what he got.

I think you're wrong about the circuit slowing down since all the
shifters are being parallel clocked, making the delays per stage
equal except for skew.

Simulate it for yourself, it's easy enough to do. all you have to do
is edit the sim I posted by replacing the Ors with diodes and a
pullup, and run it.

I'm not following you. The registers don't dominate the delay, the
logic does. All the logic feeds one FF. The more inputs to the logic
the slower it gets.


The entire point of an LFSR is that the logic is small and simple with a
very short prop delay allowing fast speeds.

---
That's a rather myopic viewpoint since the main use of an LFSR, I
believe, is to generate a pseudo-random sequence regardless of the
rate at which it's doing so.

Really? There are many ways of generating PRS. There are trade-offs
with each one. If you don't need the speed or small size an LFSR has
disadvantages compared to many others.

---
Like?
---

Oring all the outputs of a 64 or 128 bit register is not so fast
or simple even if done using state of the techniques such as
diode logic. lol

---
"State of the techniques"???

LOL indeed, since you don't even know how to talk about what you
don't know enough to talk about and, instead, offer up snarkiness as
a substitute for smart.

Lol. Yes, a typo makes for snarkiness. How about *state of the art*
techniques..? Yes, I was being sarcastic to illustrate the silliness of
mentioning DTL in a discussion of speed in LFSRs.

Are we done?

---
No.

There's still the issue of why you think delays are additive through
AND ed diodes, and why you think it's silly to use diode steering
when it's appropriate.

What is the cause of the delay in the circuit you describe? The real
issue is that the diode based circuit is impractical because no one
needs such a circuit stand alone using discrete parts. People use a
circuit like this in a design such as an FPGA or an ASIC where the
delays are in gates which are cumulative.

I'm pretty done with this conversation. It's not shedding any light at
this point. We are just rehashing the same stuff.

--

Rick

On Sun, 26 Apr 2015 21:40:52 -0400, rickman
wrote:

On 4/26/2015 6:29 PM, John Fields wrote:
On Sun, 26 Apr 2015 09:32:00 -0400, rickman
wrote:

On 4/25/2015 5:23 PM, John Fields wrote:
On Sat, 25 Apr 2015 15:49:06 -0400, rickman
wrote:

On 4/23/2015 8:06 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:35:38 -0400, rickman
wrote:

On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman
wrote:

On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman
wrote:

On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman
wrote:

On 4/16/2015 4:46 PM, John Fields wrote:

If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields


I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.

---
What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.

Can you post a contradictory example culled from the "larger field
of contenders" ?

I don't see where you have provided any examples to contradict.

---
I already posted a link to an 8 bit PRSG with 256 output states.

Did you miss it?

Apparently.

---
Well, then, for your perusal, here ya go:

https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0

This is hardly a "huge" counter...

---
Indeed, but the point made was to illustrate that NORing the outputs
of all of the stages preceding the rightmost and using that feedback
to force the PRSG into and out of the lockup state would cause it to
visit all of the 2^n possible states for that length of PRSG.

Uh, I had already indicated that this was possible and posted a link to
Peter Alfkie's app note about this for small LFSRs. So you are
restating my point.

---
As I recall, the schematic your link pointed to was a little
confusing - to me, anyway - so I decided to post something better
organized in order to illustrate the concept more clearly, not to
mention a working simulation. Which, BTW, neither you nor Alfkie
presented.

In any case, just for your information, that circuit's been around
since at least the late '60s, when I first came across it being used
as a bias-free scrambler.
---




Faulting the example because the counter isn't huge is disingenuous
since, if the lockup state is needed as part of the pattern, all
that's really needed to scale up to any PRSG length is a bunch of
diodes, a pullup resistor to Vcc, and an inverter on the outputs of
the diodes.

A bunch of diodes? I guess so, but the speed issue still remains.

---
How so?

if the diodes are all commoned on one end and followed by an
inverter, then the worst case delay will be one gate plus one diode,
which should be less than the delay through a stage of shift and
then back to the input through an EXOR.

The speed of your breadboard circuit is not really relevant. The speed
of a VLSI ASIC or an FPGA is what 99.999% of people will care about.
There is a reason why DTL is no longer used. Besides, the circuit slows
down with every diode added.

---
If you go back to the beginning, you'll see that my offering was in
reference to Jim's request for a circuit which was to be simulated
in 74XX, so that's what he got.

I think you're wrong about the circuit slowing down since all the
shifters are being parallel clocked, making the delays per stage
equal except for skew.

Simulate it for yourself, it's easy enough to do. all you have to do
is edit the sim I posted by replacing the Ors with diodes and a
pullup, and run it.

I'm not following you. The registers don't dominate the delay, the
logic does. All the logic feeds one FF. The more inputs to the logic
the slower it gets.


The entire point of an LFSR is that the logic is small and simple with a
very short prop delay allowing fast speeds.

---
That's a rather myopic viewpoint since the main use of an LFSR, I
believe, is to generate a pseudo-random sequence regardless of the
rate at which it's doing so.

Really? There are many ways of generating PRS. There are trade-offs
with each one. If you don't need the speed or small size an LFSR has
disadvantages compared to many others.

---
Like?
---

Oring all the outputs of a 64 or 128 bit register is not so fast
or simple even if done using state of the techniques such as
diode logic. lol

---
"State of the techniques"???

LOL indeed, since you don't even know how to talk about what you
don't know enough to talk about and, instead, offer up snarkiness as
a substitute for smart.

Lol. Yes, a typo makes for snarkiness. How about *state of the art*
techniques..? Yes, I was being sarcastic to illustrate the silliness of
mentioning DTL in a discussion of speed in LFSRs.

Are we done?

---
No.

There's still the issue of why you think delays are additive through
AND ed diodes, and why you think it's silly to use diode steering
when it's appropriate.

What is the cause of the delay in the circuit you describe?

---
In the counting chain it's going to be prop delays through the
flip-flops and 3 EXOR gate delays which will be cumulative.

In the pulse stuffer it's going to be one diode delay and one EXOR
which is already accounted for, so it'll simply be a single diode
delay added to the total delay through the chain.
---

The real issue is that the diode based circuit is impractical because no one
needs such a circuit stand alone using discrete parts.

---
First it was cumulative diode delay, and now you've changed horses
in mid stream and it's impractical because no one needs it since it
uses discrete parts.

Hmmm... What next?
---

People use a circuit like this in a design such as an FPGA or an ASIC where the
delays are in gates which are cumulative.

---
Could you give me an example, please? a schematic would be nice.
---

I'm pretty done with this conversation. It's not shedding any light at
this point. We are just rehashing the same stuff.

---
Bye...

Oh, BTW, for your enjoyment, here's a link:

https://www.dropbox.com/sh/gu99v7rgt...kG3J8Edea?dl=0

to an 8 bit PRSG using real-world parts with a diode
pulse-stuffer,no lockup state, and a 256 bit (2^n)cycle length.

Just download all of the files into the same folder and run the .asc
file.

John Fields

On Sun, 26 Apr 2015 09:32:00 -0400, rickman
wrote:

snip

Really? There are many ways of generating PRS. There are trade-offs
with each one. If you don't need the speed or small size an LFSR has
disadvantages compared to many others.

I hesitate to get into this, err, "discussion", but in
software at least, an LFSR has one nifty advantage over the
simpler and more-common linear congruential approach: You
can run it backwards!

Why would you want to do this? Well, one fun application is
to run two identical LFSRs in parallel and sum their
outputs to produce comb-filtered noise, where the offset
between the two LFSR sequences controls the the periodicity.
Then you can modulate the offset of one stream to slowly
sweep ahead and behind the other to get a "flanger" effect.

See "Comb Filtering and 'Flanger' Effects" at
http://www.daqarta.com/dw_0aff.htm

Best regards,


Bob Masta

DAQARTA v7.60
Data AcQuisition And Real-Time Analysis
www.daqarta.com
Scope, Spectrum, Spectrogram, Sound Level Meter
Frequency Counter, Pitch Track, Pitch-to-MIDI
FREE Signal Generator, DaqMusiq generator
Science with your sound card!

On Sun, 26 Apr 2015 15:45:09 -0700, Jim Thompson
wrote:

On Sun, 26 Apr 2015 17:32:28 -0500, John Fields
wrote:

On Sun, 26 Apr 2015 09:32:28 -0400, rickman
wrote:

On 4/25/2015 6:03 PM, John Fields wrote:
On Sat, 25 Apr 2015 15:49:45 -0400, rickman
wrote:

On 4/23/2015 8:44 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:42:23 -0400, rickman
wrote:

On 4/19/2015 3:15 AM, John Fields wrote:
On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

I'm not sure what you are going on about. Jasen's circuit does visit
every value from 0 to 65535 and does not visit 65536. In fact, if you
set it to 65536 it remains locked in that state. I think your analysis
is faulty... or mine is. I coded it up in a spread sheet and don't see
any problems with it.

---
Code is often beguiling, hardware is not.

For a 16 bit PRSG, setting it to 65536 is the same as setting it to
all zeroes, and unless there's feedback provided to lift it out of
lockup, that's where it'll stay.

You seem to have run off into the weeds on this one.

---
Perhaps, but first of all, there's this:

DECIMAL BINARY
-------+---------------------
65535 1111 1111 1111 1111

So it should be apparent that it's impossible to set, or count to
decimal 65536 using a 16 bit register.

One extra count, to 65536, will result in the counter overflowing,
the MSB dropping into the bit bucket, and the counter's output
looking like this:

DECIMAL BINARY
-------+---------------------
65536 0000 0000 0000 0000

Get it?

Like I said, off in the weeds.

---
Nice dodge.

John Fields

There is no value-added by trying to educate the effete.

...Jim Thompson

But they amuse themselves with their endless squabbling over,
basically, nothing.


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On 2015-04-27, Bob Masta wrote:
On Sun, 26 Apr 2015 09:32:00 -0400, rickman
wrote:

snip

Really? There are many ways of generating PRS. There are trade-offs
with each one. If you don't need the speed or small size an LFSR has
disadvantages compared to many others.

I hesitate to get into this, err, "discussion", but in
software at least, an LFSR has one nifty advantage over the
simpler and more-common linear congruential approach: You
can run it backwards!

You can run a linear congruential backwards it's just a matter of
using different factor and addend constants.


--
umop apisdn

On Tue, 28 Apr 2015 17:15:27 +1000, Jasen Betts wrote:

On 2015-04-27, Bob Masta wrote:
On Sun, 26 Apr 2015 09:32:00 -0400, rickman
wrote:

snip

Really? There are many ways of generating PRS. There are trade-offs
with each one. If you don't need the speed or small size an LFSR has
disadvantages compared to many others.

I hesitate to get into this, err, "discussion", but in
software at least, an LFSR has one nifty advantage over the
simpler and more-common linear congruential approach: You
can run it backwards!

You can run a linear congruential backwards it's just a matter of
using different factor and addend constants.



I've never seen that. I would like to.

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

Only vaguely on-topic, here is a noise generator experiment. The mess
on the left makes 1-bit digital noise clocked at 1 MHz, like a linear
shift register, just easier to draw. The issue at hand is what kind of
lowpass filter to use to get approximately Gaussian noise.

The 200 KHz filter is right out of AoE3 p 559. It looks fine in the
audio frequency domain, but it's nothing like Gaussian.

The 3-pole filter is a lot nicer.

We're actually going to use a LFSR in an FPGA and do the serious
filtering digitally, and drive a DAC with a little analog filtering
afterwards.


Version 4
SHEET 1 1316 680
WIRE 912 -64 848 -64
WIRE 1056 -64 912 -64
WIRE 1200 -64 1136 -64
WIRE 1248 -64 1200 -64
WIRE 1312 -64 1248 -64
WIRE 1200 -16 1200 -64
WIRE 368 64 208 64
WIRE 480 64 368 64
WIRE 208 96 208 64
WIRE 1200 96 1200 48
WIRE 720 112 656 112
WIRE 752 112 720 112
WIRE 432 128 400 128
WIRE 480 128 432 128
WIRE 208 208 208 176
WIRE 848 208 848 -64
WIRE 912 208 848 208
WIRE 1056 208 992 208
WIRE 1200 208 1136 208
WIRE 1248 208 1200 208
WIRE 1312 208 1248 208
WIRE 848 240 848 208
WIRE 400 256 400 128
WIRE 1200 256 1200 208
WIRE 400 368 400 336
WIRE 848 368 848 320
WIRE 1200 368 1200 320
FLAG 208 208 0
FLAG 368 64 NOISE
FLAG 400 368 0
FLAG 720 112 SH
FLAG 848 368 0
FLAG 912 -64 COMP
FLAG 1200 368 0
FLAG 1248 208 LPF2
FLAG 432 128 CLK
FLAG 1200 96 0
FLAG 1248 -64 LPF1
SYMBOL bv 208 80 R0
WINDOW 0 -63 105 Left 2
WINDOW 3 -131 174 Left 2
SYMATTR InstName B1
SYMATTR Value V=random(1.83e7*time) - 0.5
SYMBOL SpecialFunctions\\sample 560 96 R0
SYMATTR InstName A1
SYMBOL voltage 400 240 R0
WINDOW 0 -85 76 Left 2
WINDOW 3 -323 114 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 0 0 500n 1u)
SYMBOL bv 848 224 R0
WINDOW 0 -120 42 Left 2
WINDOW 3 -187 87 Left 2
SYMATTR InstName B2
SYMATTR Value V=sgn(v(sh))
SYMBOL res 1152 192 R90
WINDOW 0 69 58 VBottom 2
WINDOW 3 75 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL cap 1184 256 R0
WINDOW 0 51 15 Left 2
WINDOW 3 50 51 Left 2
SYMATTR InstName C1
SYMATTR Value 5n
SYMBOL res 1152 -80 R90
WINDOW 0 69 58 VBottom 2
WINDOW 3 75 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 5K
SYMBOL cap 1184 -16 R0
WINDOW 0 51 15 Left 2
WINDOW 3 50 51 Left 2
SYMATTR InstName C2
SYMATTR Value 150p
SYMBOL ind 896 224 R270
WINDOW 0 -33 54 VTop 2
WINDOW 3 -39 51 VBottom 2
SYMATTR InstName L1
SYMATTR Value 17m
TEXT 552 -48 Left 2 !.tran 25m
TEXT 216 -72 Left 2 ;Noise Generator Test
TEXT 208 -32 Left 2 ;J Larkin April 28, 2015
TEXT 432 240 Left 2 ;1 MHz CLOCK
TEXT 640 352 Left 2 ;COMPARATOR
TEXT 1056 48 Left 2 ;200 KHz
TEXT 1056 312 Left 2 ;20 KHz
TEXT 864 56 Left 2 ;DIGITAL
TEXT 864 88 Left 2 ;NOISE



--

John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

Er, well.. surely an LFSR will be flat, not Gaussian, no?

Fortunately, there is an app\\\ transform for that:
http://www.design.caltech.edu/erik/Misc/Gaussian.html
shouldn't be too bad to implement on FPGA. Log can be very crudely
obtained as the highest active ('1') bit position, and can be improved
iteratively (by repeated squarings and bit-shifts, or Taylor series
polynomial approximation methods).

Obviously, to shoot it out of a DAC, the bounds must be strictly limited,
so part of your spec will be how many sigma of Gaussian it's good for
(usually 3 or so?).

Which, in turn, implies that the argument of the log can't be near zero
(which is what produces the peaky outliers), and certainly can't be zero
exactly (which would be undefined), so perhaps the LFSR's inherent bias
could be tuned to match the dynamic range of the desired output? Nah,
probably not, not for any reasonable sequence length. So you'll have to
do something ugly (and hopefully not badly behaved), like RND * scale +
offset.

There are also methods for that -- ensuring that an output of truncated,
arbitrary range is calculated correctly from an even distribution in some
other range.

The geometric form is interesting, too; a random time delay could trigger
a S&H of complementary (90 degree phase shifted) sine waves, and the other
random number could feed a suitable arrangement of matched diode junctions
or OTAs which computes the sqrt(ln(x)) function, and simultaneously
controls the gain on the S&H buffers.

The "random" time delay has a strictly bounded range, so it could be
triggered on a fixed clock, 'computed', then 'registered' with a second
S&H on the following clock pulse, to give regularly sampled outputs (same
as you'd use extra D-flops to neaten up the transitions in a digital logic
circuit). Who even needs a DAC?

Or you could randomly sample a sin/cos table and vary the VREF into an
MDAC, or...

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com

"John Larkin" wrote in message
...
On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

Only vaguely on-topic, here is a noise generator experiment. The mess
on the left makes 1-bit digital noise clocked at 1 MHz, like a linear
shift register, just easier to draw. The issue at hand is what kind of
lowpass filter to use to get approximately Gaussian noise.

The 200 KHz filter is right out of AoE3 p 559. It looks fine in the
audio frequency domain, but it's nothing like Gaussian.

The 3-pole filter is a lot nicer.

We're actually going to use a LFSR in an FPGA and do the serious
filtering digitally, and drive a DAC with a little analog filtering
afterwards.


Version 4
SHEET 1 1316 680
WIRE 912 -64 848 -64
WIRE 1056 -64 912 -64
WIRE 1200 -64 1136 -64
WIRE 1248 -64 1200 -64
WIRE 1312 -64 1248 -64
WIRE 1200 -16 1200 -64
WIRE 368 64 208 64
WIRE 480 64 368 64
WIRE 208 96 208 64
WIRE 1200 96 1200 48
WIRE 720 112 656 112
WIRE 752 112 720 112
WIRE 432 128 400 128
WIRE 480 128 432 128
WIRE 208 208 208 176
WIRE 848 208 848 -64
WIRE 912 208 848 208
WIRE 1056 208 992 208
WIRE 1200 208 1136 208
WIRE 1248 208 1200 208
WIRE 1312 208 1248 208
WIRE 848 240 848 208
WIRE 400 256 400 128
WIRE 1200 256 1200 208
WIRE 400 368 400 336
WIRE 848 368 848 320
WIRE 1200 368 1200 320
FLAG 208 208 0
FLAG 368 64 NOISE
FLAG 400 368 0
FLAG 720 112 SH
FLAG 848 368 0
FLAG 912 -64 COMP
FLAG 1200 368 0
FLAG 1248 208 LPF2
FLAG 432 128 CLK
FLAG 1200 96 0
FLAG 1248 -64 LPF1
SYMBOL bv 208 80 R0
WINDOW 0 -63 105 Left 2
WINDOW 3 -131 174 Left 2
SYMATTR InstName B1
SYMATTR Value V=random(1.83e7*time) - 0.5
SYMBOL SpecialFunctions\\sample 560 96 R0
SYMATTR InstName A1
SYMBOL voltage 400 240 R0
WINDOW 0 -85 76 Left 2
WINDOW 3 -323 114 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 0 0 500n 1u)
SYMBOL bv 848 224 R0
WINDOW 0 -120 42 Left 2
WINDOW 3 -187 87 Left 2
SYMATTR InstName B2
SYMATTR Value V=sgn(v(sh))
SYMBOL res 1152 192 R90
WINDOW 0 69 58 VBottom 2
WINDOW 3 75 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL cap 1184 256 R0
WINDOW 0 51 15 Left 2
WINDOW 3 50 51 Left 2
SYMATTR InstName C1
SYMATTR Value 5n
SYMBOL res 1152 -80 R90
WINDOW 0 69 58 VBottom 2
WINDOW 3 75 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 5K
SYMBOL cap 1184 -16 R0
WINDOW 0 51 15 Left 2
WINDOW 3 50 51 Left 2
SYMATTR InstName C2
SYMATTR Value 150p
SYMBOL ind 896 224 R270
WINDOW 0 -33 54 VTop 2
WINDOW 3 -39 51 VBottom 2
SYMATTR InstName L1
SYMATTR Value 17m
TEXT 552 -48 Left 2 !.tran 25m
TEXT 216 -72 Left 2 ;Noise Generator Test
TEXT 208 -32 Left 2 ;J Larkin April 28, 2015
TEXT 432 240 Left 2 ;1 MHz CLOCK
TEXT 640 352 Left 2 ;COMPARATOR
TEXT 1056 48 Left 2 ;200 KHz
TEXT 1056 312 Left 2 ;20 KHz
TEXT 864 56 Left 2 ;DIGITAL
TEXT 864 88 Left 2 ;NOISE



--

John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On 2015-04-29, David Eather wrote:
On Tue, 28 Apr 2015 17:15:27 +1000, Jasen Betts wrote:

On 2015-04-27, Bob Masta wrote:
On Sun, 26 Apr 2015 09:32:00 -0400, rickman
wrote:

snip

Really? There are many ways of generating PRS. There are trade-offs
with each one. If you don't need the speed or small size an LFSR has
disadvantages compared to many others.

I hesitate to get into this, err, "discussion", but in
software at least, an LFSR has one nifty advantage over the
simpler and more-common linear congruential approach: You
can run it backwards!

You can run a linear congruential backwards it's just a matter of
using different factor and addend constants.


I've never seen that. I would like to.


#include stdio.h

unsigned int seed=1;

/* a common LC random */
unsigned int rand(void){
seed= ((long long) seed*1103515245 + 12345 ) &0xfffffffful;
return seed;
}

/* the inverse */
unsigned int unrand(void){
seed=((long long) seed *4005161829 + 4235699843) &0xfffffffful ;
return seed;
}

/*

4005161829 above is the reciprocal of 1103515245 mod 2^32

knowing that multiplication by 1103515245 would have a period of 2^32
in mod 2^32

I asked wolfram alpha "1103515245 ^4294967295 mod 4294967296"


4235699843 above is the additive inverse of 12345 * 4005161829 mod 2^32

I asked wolfram alpha
"4294967296 - (( 12345 * 4005161829 ) mod 4294967296 )"

modular arithmetic is crazy stuff...

*/

main(){
int x;

printf("%10u ",seed); printf(" %10u\n", rand());
printf("%10u ",seed); printf(" %10u\n", rand());
printf("%10u ",seed); printf(" %10u\n", rand());
printf("%10u ",seed); printf(" %10u\n", rand());
printf("%10u ",seed); printf(" %10u\n", rand());
printf("%10u ",seed); printf(" %10u\n", rand());
printf("--------------------\n");
printf("%10u ",seed); printf(" %10u\n", unrand());
printf("%10u ",seed); printf(" %10u\n", unrand());
printf("%10u ",seed); printf(" %10u\n", unrand());
printf("%10u ",seed); printf(" %10u\n", unrand());
printf("%10u ",seed); printf(" %10u\n", unrand());
printf("%10u ",seed); printf(" %10u\n", unrand());
printf("--------------------\n");

seed=8008135;
printf("%10u ",seed);
for( x=1; x 10000000; ++x ) rand();
printf("%10u\n",seed);
printf("%10u ",seed);
for( x=1; x 10000000; ++x ) unrand();
printf("%10u\n",seed);
return 0;
}


--
umop apisdn

On Tue, 28 Apr 2015 21:38:58 -0700, John Larkin
wrote:

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

Only vaguely on-topic, here is a noise generator experiment. The mess
on the left makes 1-bit digital noise clocked at 1 MHz, like a linear
shift register, just easier to draw. The issue at hand is what kind of
lowpass filter to use to get approximately Gaussian noise.

The 200 KHz filter is right out of AoE3 p 559. It looks fine in the
audio frequency domain, but it's nothing like Gaussian.

The 3-pole filter is a lot nicer.

We're actually going to use a LFSR in an FPGA and do the serious
filtering digitally, and drive a DAC with a little analog filtering
afterwards.

I have a Daqarta "mini-app" for converting a uniform to an
arbitrary distribution. I use Gaussian as the example. The
Help page is at
http://www.daqarta.com/dw_0oaa.htm. It includes a
"Theory" section, plus the complete macro script (it's in
Daqarta's own macro language, but I've added lots of
comments).

The basic method uses the inverse Cumulative Distribution
Function (iCDF) with a lookup table. The trick is to create
the proper table.

Best regards,


Bob Masta

DAQARTA v7.60
Data AcQuisition And Real-Time Analysis
www.daqarta.com
Scope, Spectrum, Spectrogram, Sound Level Meter
Frequency Counter, Pitch Track, Pitch-to-MIDI
FREE Signal Generator, DaqMusiq generator
Science with your sound card!

On Wed, 29 Apr 2015 02:16:52 -0500, "Tim Williams"
wrote:

Er, well.. surely an LFSR will be flat, not Gaussian, no?

Single bit digital noise has a PDF with two big impulses, about the
worst approximation to Gaussian (or flat) imaginable. So you need to
sum a LOT of them to get something sort of Gaussian... the Central
Limit Theorem thing. Hence the 20 KHz filter. Higher-order filters
work way better than single-pole ones.

If you nab 16-bit words from the shift register, and not the single
bit, you start with a basically flat histogram. Summing a modest
number of them gets Gaussian pretty fast. That's harder to Spice.


Fortunately, there is an app\\\ transform for that:
http://www.design.caltech.edu/erik/Misc/Gaussian.html
shouldn't be too bad to implement on FPGA. Log can be very crudely
obtained as the highest active ('1') bit position, and can be improved
iteratively (by repeated squarings and bit-shifts, or Taylor series
polynomial approximation methods).

Obviously, to shoot it out of a DAC, the bounds must be strictly limited,
so part of your spec will be how many sigma of Gaussian it's good for
(usually 3 or so?).

We have a +-10 volt DAC range, and we figure that 1 volt RMS is a good
number, and our 15-tap FIR filter will give us a crest factor of about
5.5. That sounds OK; I don't think our customers would want truly
Gaussian noise with infinite voltage spikes.


Which, in turn, implies that the argument of the log can't be near zero
(which is what produces the peaky outliers), and certainly can't be zero
exactly (which would be undefined), so perhaps the LFSR's inherent bias
could be tuned to match the dynamic range of the desired output? Nah,
probably not, not for any reasonable sequence length. So you'll have to
do something ugly (and hopefully not badly behaved), like RND * scale +
offset.

There are also methods for that -- ensuring that an output of truncated,
arbitrary range is calculated correctly from an even distribution in some
other range.

The geometric form is interesting, too; a random time delay could trigger
a S&H of complementary (90 degree phase shifted) sine waves, and the other
random number could feed a suitable arrangement of matched diode junctions
or OTAs which computes the sqrt(ln(x)) function, and simultaneously
controls the gain on the S&H buffers.

The "random" time delay has a strictly bounded range, so it could be
triggered on a fixed clock, 'computed', then 'registered' with a second
S&H on the following clock pulse, to give regularly sampled outputs (same
as you'd use extra D-flops to neaten up the transitions in a digital logic
circuit). Who even needs a DAC?

Or you could randomly sample a sin/cos table and vary the VREF into an
MDAC, or...

A tapped analog delay line is easy to Spice. If you poke in random
values and evenly sum the taps, that amounts to summing a sucession of
samples, so it does the Central Limit thing for you. And it's also a
finite-impulse-response filter. Everything turns out the be the same
thing, just looked at from different angles.

I really need a histogram back end for LT Spice. Snarl, snap, I guess
I'll have to make one.


--

John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Wed, 01 Apr 2015 12:06:00 -0700, John Larkin
wrote:

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

http://www.theregister.co.uk/2015/04...andom_numbers/

--
Boris

---
This email has been checked for viruses by Avast antivirus software.
http://www.avast.com

On Sat, 25 Apr 2015 11:17:52 +1000, "David Eather"
wrote:


A paraphrase:
"anyone who believes a deterministic circuit can produce true randomness
is in a state of sin"

---
Beautiful.

John Fields

Jim Thompson
Wrote in message:
On Wed, 01 Apr 2015 11:53:10 -0700, Jim Thompson
wrote:

On Wed, 01 Apr 2015 13:27:06 -0500, John Fields
wrote:

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

---
If you use something like an HC154 with an LFSR driving its address
inputs to generate random one-hots on its outputs, will that work
for you?

John,

What are you saying... take the outputs of the LFSR broadside to drive
the address lines of the 'HC154?

I think that would do it.

Thanks also to Lasse for the same suggestion.

...Jim Thompson

I was puzzling over how to get 0000, but then it dawned... just use an
8-bit LFSR and use the last 4-bits.

It would be less than random because 0000 is still less likely.
Better to use a fast counter and latch it before the
154.

Because it's not physical maybe you'd have to jiggle the fast
clock with a large resistor to one of the bits, if Spice would
have a tendency to make one clock an exact multiple of the other.


--

On Wed, 27 Apr 2016 15:19:18 -0400 (EDT), Tom Del Rosso
wrote:

Jim Thompson
Wrote in message:
On Wed, 01 Apr 2015 11:53:10 -0700, Jim Thompson
wrote:

On Wed, 01 Apr 2015 13:27:06 -0500, John Fields
wrote:

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

---
If you use something like an HC154 with an LFSR driving its address
inputs to generate random one-hots on its outputs, will that work
for you?

John,

What are you saying... take the outputs of the LFSR broadside to drive
the address lines of the 'HC154?

I think that would do it.

Thanks also to Lasse for the same suggestion.

...Jim Thompson

I was puzzling over how to get 0000, but then it dawned... just use an
8-bit LFSR and use the last 4-bits.

It would be less than random because 0000 is still less likely.
Better to use a fast counter and latch it before the
154.

Because it's not physical maybe you'd have to jiggle the fast
clock with a large resistor to one of the bits, if Spice would
have a tendency to make one clock an exact multiple of the other.


Did you notice you're replying to a YEAR OLD post ?:-)

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

The touchstone of liberalism is intolerance

Tom Del Rosso wrote:



I was puzzling over how to get 0000, but then it dawned... just use an
8-bit LFSR and use the last 4-bits.
OK, you don't want to just use the last N bits of the LFSR, as they will
shift over VERY predictably. So, if you want to use N bits, you need to
allow the LFSR to advance N clocks and then latch the N parallel bits for
use.

Jon

Jim Thompson wrote:

Did you notice you're replying to a YEAR OLD post ?:-)

On the phone app it wasn't so obvious. I don't use it much but it was
updated a month ago so I don't know why this thread was near the top.