On Sat, 18 Apr 2015 18:29:50 -0700, John Larkin
wrote:

On Sat, 18 Apr 2015 21:16:52 -0400, krw wrote:

On Sat, 18 Apr 2015 17:32:51 -0700, John Larkin
wrote:

On Sat, 18 Apr 2015 17:35:20 -0500, John Fields
wrote:

On Fri, 17 Apr 2015 10:43:42 -0700, John Larkin
wrote:

On Thu, 16 Apr 2015 23:14:35 -0500, John Fields
wrote:

On Thu, 16 Apr 2015 10:47:36 -0700, John Larkin
wrote:


These are electronics newsgroups.

---
And, as such, your narcissistic off-topic garbage has no proper
place here.
---

We do seem to have a faction of
ancient cackling farts who only want to gossip and whine about
personalities, and drone out insults, and haven't touched a soldering
iron in years, or decades.

---
Some of us have progressed past the soldering iron stage


Now that's really sad. What do you do all day, argue and whine on
newsgroups?

---
Funny you should ask - since you've already made up your mind - but
no; I do heavy-duty innovative circuit design instead of
paint-by-number engineering.

Cool. Tell us about what you're working on.

A new 555 circuit.

Is that possible?

---
To a mind which is closed, probably not.

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

On Sun, 19 Apr 2015 00:00:40 -0400, krw wrote:

On Sat, 18 Apr 2015 18:29:50 -0700, John Larkin
wrote:

On Sat, 18 Apr 2015 21:16:52 -0400, krw wrote:

On Sat, 18 Apr 2015 17:32:51 -0700, John Larkin
wrote:

On Sat, 18 Apr 2015 17:35:20 -0500, John Fields
wrote:

On Fri, 17 Apr 2015 10:43:42 -0700, John Larkin
wrote:

On Thu, 16 Apr 2015 23:14:35 -0500, John Fields
wrote:

On Thu, 16 Apr 2015 10:47:36 -0700, John Larkin
wrote:


These are electronics newsgroups.

---
And, as such, your narcissistic off-topic garbage has no proper
place here.
---

We do seem to have a faction of
ancient cackling farts who only want to gossip and whine about
personalities, and drone out insults, and haven't touched a soldering
iron in years, or decades.

---
Some of us have progressed past the soldering iron stage


Now that's really sad. What do you do all day, argue and whine on
newsgroups?

---
Funny you should ask - since you've already made up your mind - but
no; I do heavy-duty innovative circuit design instead of
paint-by-number engineering.

Cool. Tell us about what you're working on.

A new 555 circuit.

Is that possible?

That's why the job is so heavy duty.

---
Omigod, Heckle and Jeckle are at it again...

On Sun, 19 Apr 2015 10:42:05 +1000, "David Eather"
wrote:

On Sun, 19 Apr 2015 09:00:58 +1000, John Fields
wrote:

On Sat, 18 Apr 2015 22:15:13 +1000, "David Eather"
wrote:

On Sat, 18 Apr 2015 20:30:31 +1000, Jasen Betts
wrote:

On 2015-04-18, rickman wrote:
On 4/17/2015 10:56 PM, Jasen Betts wrote:
On 2015-04-17, rickman wrote:
On 4/17/2015 7:51 AM, Jasen Betts wrote:

one 16 bit - 7 bit subtract
one 16 bit + 0 bit add with carry.

I'm not following. Are you saying a modulo 65537 operation can be
done
with two adders?

yes.

I appreciate the effort in the drawing, but that isn't needed.
Knowing
that you use adders doesn't help me understand how the arithmetic
works.
Is there a simple explanation? BTW, what do you do with bit 16 on
the
input? Is that a typo? Does it go with the lsbs or the msbs?

It's a typo (or a fence-post error).

this is the arithmetic in c:

// a=a % 65537 in c:

a = a & 0xffff - ( a & ~ 0xffff ) 16;
a = a0 ? a & 0xffff + 1 : a ;


Its an abortive mistake.

It should be mod 2^n i.e. 65536. or 256 or 16 etc

also you don't use a rotation just a left shift. Each left shift by 1
bit
works like a multiply *2 and you don't need to track the carry outs or
MSB's of the shifted number the mod function throws them away anyway.

So to use an adder to multiply by say 5 you have the input number feed
into one input of the adder shifted left by 2 bits - that is 4 x the
input
number. Into the other input of the adder you input the original seed -
so
4 x the input number plus the input number = 5 x the input number. If
the
modulus function is a power of 2 then discarding the right number of
MSB's
take care of that - you don't even have to feed them into the adder
since
the result will be discarded anyway.

Last if you use the carry in of the least significant adder as a + 1
function then a simple LCG takes one adder only (excluding latches you
might need to avoid race issues)

---
So you have to use a shifter, adders, latches, and some glue logic
to get to 2^n?

NO shifter, repeat NO shifter, and total glue logic equals 1 inverter.


How is that simpler than using a shifter, a few EXORs and a NOR to
do the same thing?

John Fields

No it does not do the same thing.

I like LFSR but they may not work in the specific case Jim asked for.

A LFSR does not produce all possible output states - it will not produce
all zeros or all ones depending on the configuration. This means that it
may cause the AGC control voltage to drift high or low until it rails.
Which rather wrecks Jim's simulation.

---
The circuit I posted suffers from no such limitation.
---

On the other hand and LCG as I described produces every possible state
once per cycle and will not have a potential problem if used to control
and AGC.

Since it is for simulation, the cost of an LCG is not an issue and it only
takes a small time to implement.

---
And the circuit I posted doesn't?
---

QED.

---
Not QED until you post a simulation and demonstrate that the machine
works as postulated.

Instead of just talking about what you've got, why not post some
proof?

On Sun, 19 Apr 2015 17:34:26 +1000, John Fields
wrote:

On Sun, 19 Apr 2015 10:42:05 +1000, "David Eather"
wrote:

On Sun, 19 Apr 2015 09:00:58 +1000, John Fields
wrote:

On Sat, 18 Apr 2015 22:15:13 +1000, "David Eather"
wrote:

On Sat, 18 Apr 2015 20:30:31 +1000, Jasen Betts
wrote:

On 2015-04-18, rickman wrote:
On 4/17/2015 10:56 PM, Jasen Betts wrote:
On 2015-04-17, rickman wrote:
On 4/17/2015 7:51 AM, Jasen Betts wrote:

one 16 bit - 7 bit subtract
one 16 bit + 0 bit add with carry.

I'm not following. Are you saying a modulo 65537 operation can be
done
with two adders?

yes.

I appreciate the effort in the drawing, but that isn't needed.
Knowing
that you use adders doesn't help me understand how the arithmetic
works.
Is there a simple explanation? BTW, what do you do with bit 16 on
the
input? Is that a typo? Does it go with the lsbs or the msbs?

It's a typo (or a fence-post error).

this is the arithmetic in c:

// a=a % 65537 in c:

a = a & 0xffff - ( a & ~ 0xffff ) 16;
a = a0 ? a & 0xffff + 1 : a ;


Its an abortive mistake.

It should be mod 2^n i.e. 65536. or 256 or 16 etc

also you don't use a rotation just a left shift. Each left shift by 1
bit
works like a multiply *2 and you don't need to track the carry outs or
MSB's of the shifted number the mod function throws them away anyway.

So to use an adder to multiply by say 5 you have the input number feed
into one input of the adder shifted left by 2 bits - that is 4 x the
input
number. Into the other input of the adder you input the original seed
-
so
4 x the input number plus the input number = 5 x the input number. If
the
modulus function is a power of 2 then discarding the right number of
MSB's
take care of that - you don't even have to feed them into the adder
since
the result will be discarded anyway.

Last if you use the carry in of the least significant adder as a + 1
function then a simple LCG takes one adder only (excluding latches you
might need to avoid race issues)

---
So you have to use a shifter, adders, latches, and some glue logic
to get to 2^n?

NO shifter, repeat NO shifter, and total glue logic equals 1 inverter.


How is that simpler than using a shifter, a few EXORs and a NOR to
do the same thing?

John Fields

No it does not do the same thing.

I like LFSR but they may not work in the specific case Jim asked for.

A LFSR does not produce all possible output states - it will not produce
all zeros or all ones depending on the configuration. This means that it
may cause the AGC control voltage to drift high or low until it rails.
Which rather wrecks Jim's simulation.

---
The circuit I posted suffers from no such limitation.
---

On the other hand and LCG as I described produces every possible state
once per cycle and will not have a potential problem if used to control
and AGC.

Since it is for simulation, the cost of an LCG is not an issue and it
only
takes a small time to implement.

---
And the circuit I posted doesn't?
---

QED.

---
Not QED until you post a simulation and demonstrate that the machine
works as postulated.

Instead of just talking about what you've got, why not post some
proof?


I posted links in this thread twice.

On Sun, 19 Apr 2015 01:53:24 -0500, John Fields
wrote:

On Sat, 18 Apr 2015 17:32:51 -0700, John Larkin
wrote:

On Sat, 18 Apr 2015 17:35:20 -0500, John Fields
wrote:

On Fri, 17 Apr 2015 10:43:42 -0700, John Larkin
wrote:

On Thu, 16 Apr 2015 23:14:35 -0500, John Fields
wrote:

On Thu, 16 Apr 2015 10:47:36 -0700, John Larkin
wrote:


These are electronics newsgroups.

---
And, as such, your narcissistic off-topic garbage has no proper
place here.
---

We do seem to have a faction of
ancient cackling farts who only want to gossip and whine about
personalities, and drone out insults, and haven't touched a soldering
iron in years, or decades.

---
Some of us have progressed past the soldering iron stage


Now that's really sad. What do you do all day, argue and whine on
newsgroups?

---
Funny you should ask - since you've already made up your mind - but
no; I do heavy-duty innovative circuit design instead of
paint-by-number engineering.

Cool. Tell us about what you're working on.

---
Sorry, loose lips sink ships...

John Fields

Oh, if it's a matter of national security, by all means keep it
secret.


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Mon, 20 Apr 2015 10:28:46 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 01:53:24 -0500, John Fields
wrote:

On Sat, 18 Apr 2015 17:32:51 -0700, John Larkin
wrote:

On Sat, 18 Apr 2015 17:35:20 -0500, John Fields
wrote:

On Fri, 17 Apr 2015 10:43:42 -0700, John Larkin
wrote:

On Thu, 16 Apr 2015 23:14:35 -0500, John Fields
wrote:

On Thu, 16 Apr 2015 10:47:36 -0700, John Larkin
wrote:


These are electronics newsgroups.

---
And, as such, your narcissistic off-topic garbage has no proper
place here.
---

We do seem to have a faction of
ancient cackling farts who only want to gossip and whine about
personalities, and drone out insults, and haven't touched a soldering
iron in years, or decades.

---
Some of us have progressed past the soldering iron stage


Now that's really sad. What do you do all day, argue and whine on
newsgroups?

---
Funny you should ask - since you've already made up your mind - but
no; I do heavy-duty innovative circuit design instead of
paint-by-number engineering.

Cool. Tell us about what you're working on.

---
Sorry, loose lips sink ships...

John Fields

Oh, if it's a matter of national security, by all means keep it
secret.

---
If it had anything to do with national security I would have made no
comment at all. But of course you know that - or at least you
should - so, other than being your usual nasty little self, what's
the reason for your gratuitous snarkiness?

John Fields
Professional Circuit Designer

On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman
wrote:

On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman
wrote:

On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman
wrote:

On 4/16/2015 4:46 PM, John Fields wrote:

If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields


I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.

---
What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.

Can you post a contradictory example culled from the "larger field
of contenders" ?

I don't see where you have provided any examples to contradict.

---
I already posted a link to an 8 bit PRSG with 256 output states.

Did you miss it?

Apparently.

---
Well, then, for your perusal, here ya go:

https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0

This is hardly a "huge" counter...

--

Rick

On 4/19/2015 3:15 AM, John Fields wrote:
On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

I'm not sure what you are going on about. Jasen's circuit does visit
every value from 0 to 65535 and does not visit 65536. In fact, if you
set it to 65536 it remains locked in that state. I think your analysis
is faulty... or mine is. I coded it up in a spread sheet and don't see
any problems with it.

--

Rick

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

https://dl.dropboxusercontent.com/u/...back_Front.JPG

We call this the Wayback Machine in remembrance of Rocky and
Bulwinkle.


--

John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Wed, 22 Apr 2015 13:35:38 -0400, rickman
wrote:

On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman
wrote:

On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman
wrote:

On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman
wrote:

On 4/16/2015 4:46 PM, John Fields wrote:

If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields


I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.

---
What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.

Can you post a contradictory example culled from the "larger field
of contenders" ?

I don't see where you have provided any examples to contradict.

---
I already posted a link to an 8 bit PRSG with 256 output states.

Did you miss it?

Apparently.

---
Well, then, for your perusal, here ya go:

https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0

This is hardly a "huge" counter...

---
Indeed, but the point made was to illustrate that NORing the outputs
of all of the stages preceding the rightmost and using that feedback
to force the PRSG into and out of the lockup state would cause it to
visit all of the 2^n possible states for that length of PRSG.

Faulting the example because the counter isn't huge is disingenuous
since, if the lockup state is needed as part of the pattern, all
that's really needed to scale up to any PRSG length is a bunch of
diodes, a pullup resistor to Vcc, and an inverter on the outputs of
the diodes.

John Fields

On Wed, 22 Apr 2015 13:42:23 -0400, rickman
wrote:

On 4/19/2015 3:15 AM, John Fields wrote:
On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

I'm not sure what you are going on about. Jasen's circuit does visit
every value from 0 to 65535 and does not visit 65536. In fact, if you
set it to 65536 it remains locked in that state. I think your analysis
is faulty... or mine is. I coded it up in a spread sheet and don't see
any problems with it.

---
Code is often beguiling, hardware is not.

For a 16 bit PRSG, setting it to 65536 is the same as setting it to
all zeroes, and unless there's feedback provided to lift it out of
lockup, that's where it'll stay.

John Fields

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields

On Thu, 23 Apr 2015 19:59:43 -0500, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields

Each 18-bit sample is taken at a time determined by the rollover of a
64-bit DDS. All the samples are piped through a 128-tap digital FIR
filter, which stirs them up pretty well. The result goes through a
16-bit DAC and an analog lowpass filter. It looks like bandlimited
Gaussian noise, and I don't think my customers are going to demand
their money back.


--

John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Thu, 23 Apr 2015 20:48:34 -0700, John Larkin
wrote:

On Thu, 23 Apr 2015 19:59:43 -0500, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields

Each 18-bit sample is taken at a time determined by the rollover of a
64-bit DDS. All the samples are piped through a 128-tap digital FIR
filter, which stirs them up pretty well. The result goes through a
16-bit DAC and an analog lowpass filter. It looks like bandlimited
Gaussian noise, and I don't think my customers are going to demand
their money back.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields

On Fri, 24 Apr 2015 06:44:47 -0500, John Fields
wrote:

On Thu, 23 Apr 2015 20:48:34 -0700, John Larkin
wrote:

On Thu, 23 Apr 2015 19:59:43 -0500, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields

Each 18-bit sample is taken at a time determined by the rollover of a
64-bit DDS. All the samples are piped through a 128-tap digital FIR
filter, which stirs them up pretty well. The result goes through a
16-bit DAC and an analog lowpass filter. It looks like bandlimited
Gaussian noise, and I don't think my customers are going to demand
their money back.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields

You seem to have lots of time for philosophical nonsense.


--

John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Fri, 24 Apr 2015 07:43:47 -0700, John Larkin
wrote:

On Fri, 24 Apr 2015 06:44:47 -0500, John Fields
wrote:

On Thu, 23 Apr 2015 20:48:34 -0700, John Larkin
wrote:

On Thu, 23 Apr 2015 19:59:43 -0500, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields

Each 18-bit sample is taken at a time determined by the rollover of a
64-bit DDS. All the samples are piped through a 128-tap digital FIR
filter, which stirs them up pretty well. The result goes through a
16-bit DAC and an analog lowpass filter. It looks like bandlimited
Gaussian noise, and I don't think my customers are going to demand
their money back.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields

You seem to have lots of time for philosophical nonsense.

---
So, in the light of that castigation, I'm wrong and your scheme
produces a truly random output?

Kinda like, from your earlier expressed but incorrect point of view,
latching relays have infinite gain.

If you'd have been paying attention, you might have noticed that
this thread started with Jim Thompson asking for a simple 4 bit
pseudo-random sequence generator for generating/testing a 16 state
datacom constellation.

Several solutions were offered but, as expected, you contested none
of them, provided no help, and waited until nearly the end to use
this channel to hawk your wares.

On Fri, 24 Apr 2015 15:06:28 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 07:43:47 -0700, John Larkin
wrote:

On Fri, 24 Apr 2015 06:44:47 -0500, John Fields
wrote:

On Thu, 23 Apr 2015 20:48:34 -0700, John Larkin
wrote:

On Thu, 23 Apr 2015 19:59:43 -0500, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields

Each 18-bit sample is taken at a time determined by the rollover of a
64-bit DDS. All the samples are piped through a 128-tap digital FIR
filter, which stirs them up pretty well. The result goes through a
16-bit DAC and an analog lowpass filter. It looks like bandlimited
Gaussian noise, and I don't think my customers are going to demand
their money back.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields

You seem to have lots of time for philosophical nonsense.

---
So, in the light of that castigation, I'm wrong and your scheme
produces a truly random output?

I have no idea what you might mean by "truly random output", and I
doubt that you do either.

That's a matter of definition and philosophy. And a waste of time.



Kinda like, from your earlier expressed but incorrect point of view,
latching relays have infinite gain.

If you'd have been paying attention, you might have noticed that
this thread started with Jim Thompson asking for a simple 4 bit
pseudo-random sequence generator for generating/testing a 16 state
datacom constellation.

Several solutions were offered but, as expected, you contested none
of them, provided no help, and waited until nearly the end to use
this channel to hawk your wares.

I'm not hawking anything. I don't expect anyone here to buy my stuff.

Hardly anyone here ever posts pics or schematics of actual products
and PC boards. You certainly don't. I wish more people would.

So, I post real schematic fragments and pictures of boards and boxes.
Hey, doing that got me into AoE3!


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Fri, 24 Apr 2015 13:26:08 -0700, John Larkin
wrote:

On Fri, 24 Apr 2015 15:06:28 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 07:43:47 -0700, John Larkin
wrote:


You seem to have lots of time for philosophical nonsense.

---
So, in the light of that castigation, I'm wrong and your scheme
produces a truly random output?

I have no idea what you might mean by "truly random output", and I
doubt that you do either.

---
Well, of course you don't and, your perception of being at the very
pinnacle of the food chain makes everything you don't understand
unimportant.
---

That's a matter of definition and philosophy. And a waste of time.

---
But your silly ramblings aren't?
---

Kinda like, from your earlier expressed but incorrect point of view,
latching relays have infinite gain.

If you'd have been paying attention, you might have noticed that
this thread started with Jim Thompson asking for a simple 4 bit
pseudo-random sequence generator for generating/testing a 16 state
datacom constellation.

Several solutions were offered but, as expected, you contested none
of them, provided no help, and waited until nearly the end to use
this channel to hawk your wares.

I'm not hawking anything. I don't expect anyone here to buy my stuff.

---
And yet the touting goes on, unabated.
---

Hardly anyone here ever posts pics or schematics of actual products
and PC boards. You certainly don't. I wish more people would.

---
I posted a working .asc of an 8 bit PRSG with no lockup states on
this very thread just a couple of days ago, and many hundreds of
finished schematics, circuit descriptions and pictures over the last
20 years or so, so I guess you're either being selectively ignorant,
have a short attention span, or you're just not paying attention.
---

So, I post real schematic fragments and pictures of boards and boxes.
Hey, doing that got me into AoE3!

---
Well, no one's perfect.

John Fields

On Fri, 24 Apr 2015 19:17:18 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 13:26:08 -0700, John Larkin
wrote:

On Fri, 24 Apr 2015 15:06:28 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 07:43:47 -0700, John Larkin
wrote:


You seem to have lots of time for philosophical nonsense.

---
So, in the light of that castigation, I'm wrong and your scheme
produces a truly random output?

I have no idea what you might mean by "truly random output", and I
doubt that you do either.

---
Well, of course you don't and, your perception of being at the very
pinnacle of the food chain makes everything you don't understand
unimportant.

Define "truly random output", and I'll tell you if my board meets your
standards.




---

That's a matter of definition and philosophy. And a waste of time.

---
But your silly ramblings aren't?
---

Kinda like, from your earlier expressed but incorrect point of view,
latching relays have infinite gain.

If you'd have been paying attention, you might have noticed that
this thread started with Jim Thompson asking for a simple 4 bit
pseudo-random sequence generator for generating/testing a 16 state
datacom constellation.

Several solutions were offered but, as expected, you contested none
of them, provided no help, and waited until nearly the end to use
this channel to hawk your wares.

I'm not hawking anything. I don't expect anyone here to buy my stuff.

---
And yet the touting goes on, unabated.

This is an electronics discussion group. We need things to discuss.
And I do a *lot* of electronics!




--

John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Fri, 24 Apr 2015 10:59:43 +1000, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts
wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat
more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an
excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields


A paraphrase:
"anyone who believes a deterministic circuit can produce true randomness
is in a state of sin"

On Sat, 25 Apr 2015 11:17:52 +1000, "David Eather"
wrote:

On Fri, 24 Apr 2015 10:59:43 +1000, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts
wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat
more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an
excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields


A paraphrase:
"anyone who believes a deterministic circuit can produce true randomness
is in a state of sin"

So, we have preceded from the philosophical to the theological.


--

John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Sat, 25 Apr 2015 12:46:57 +1000, John Larkin
wrote:

On Sat, 25 Apr 2015 11:17:52 +1000, "David Eather"
wrote:

On Fri, 24 Apr 2015 10:59:43 +1000, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts
wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat
more
than once - it not longer visits 0 - 65535 without gaps (it
outputs a
665536 which needs 17 bits) and will miss a 16 bit number every
cycle
after the first, OR if the 17-th bit is ignored it will produce an
excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields


A paraphrase:
"anyone who believes a deterministic circuit can produce true randomness
is in a state of sin"

So, we have preceded from the philosophical to the theological.



No, from speculation to Shannon.

On Sat, 25 Apr 2015 18:31:24 +1000, David Eather wrote:

On Sat, 25 Apr 2015 12:46:57 +1000, John Larkin
wrote:

On Sat, 25 Apr 2015 11:17:52 +1000, "David Eather"
wrote:

On Fri, 24 Apr 2015 10:59:43 +1000, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts
wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to
repeat
more
than once - it not longer visits 0 - 65535 without gaps (it
outputs a
665536 which needs 17 bits) and will miss a 16 bit number every
cycle
after the first, OR if the 17-th bit is ignored it will produce an
excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields


A paraphrase:
"anyone who believes a deterministic circuit can produce true
randomness
is in a state of sin"

So, we have preceded from the philosophical to the theological.



No, from speculation to Shannon.

and hence mathematical theory

On Fri, 24 Apr 2015 17:27:26 -0700, John Larkin
wrote:

On Fri, 24 Apr 2015 19:17:18 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 13:26:08 -0700, John Larkin
wrote:

On Fri, 24 Apr 2015 15:06:28 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 07:43:47 -0700, John Larkin
wrote:


You seem to have lots of time for philosophical nonsense.

---
So, in the light of that castigation, I'm wrong and your scheme
produces a truly random output?

I have no idea what you might mean by "truly random output", and I
doubt that you do either.

---
Well, of course you don't and, your perception of being at the very
pinnacle of the food chain makes everything you don't understand
unimportant.

Define "truly random output", and I'll tell you if my board meets your
standards.

---
They're not _my_ standards, John, we all live by them.

Most of us understand the concept, and you could too if Google were
your friend.
---

That's a matter of definition and philosophy. And a waste of time.

---
But your silly ramblings aren't?
---

Kinda like, from your earlier expressed but incorrect point of view,
latching relays have infinite gain.

If you'd have been paying attention, you might have noticed that
this thread started with Jim Thompson asking for a simple 4 bit
pseudo-random sequence generator for generating/testing a 16 state
datacom constellation.

Several solutions were offered but, as expected, you contested none
of them, provided no help, and waited until nearly the end to use
this channel to hawk your wares.

I'm not hawking anything. I don't expect anyone here to buy my stuff.

---
And yet the touting goes on, unabated.

This is an electronics discussion group. We need things to discuss.
And I do a *lot* of electronics!

---
What you do here is pat yourself on the back a lot.

On Sat, 25 Apr 2015 04:11:40 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 17:27:26 -0700, John Larkin
wrote:

On Fri, 24 Apr 2015 19:17:18 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 13:26:08 -0700, John Larkin
wrote:

On Fri, 24 Apr 2015 15:06:28 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 07:43:47 -0700, John Larkin
wrote:


You seem to have lots of time for philosophical nonsense.

---
So, in the light of that castigation, I'm wrong and your scheme
produces a truly random output?

I have no idea what you might mean by "truly random output", and I
doubt that you do either.

---
Well, of course you don't and, your perception of being at the very
pinnacle of the food chain makes everything you don't understand
unimportant.

Define "truly random output", and I'll tell you if my board meets your
standards.

---
They're not _my_ standards, John, we all live by them.


OK, you have no definition of "truly random."


Most of us understand the concept, and you could too if Google were
your friend.
---

That's a matter of definition and philosophy. And a waste of time.

---
But your silly ramblings aren't?
---

Kinda like, from your earlier expressed but incorrect point of view,
latching relays have infinite gain.

If you'd have been paying attention, you might have noticed that
this thread started with Jim Thompson asking for a simple 4 bit
pseudo-random sequence generator for generating/testing a 16 state
datacom constellation.

Several solutions were offered but, as expected, you contested none
of them, provided no help, and waited until nearly the end to use
this channel to hawk your wares.

I'm not hawking anything. I don't expect anyone here to buy my stuff.

---
And yet the touting goes on, unabated.

This is an electronics discussion group. We need things to discuss.
And I do a *lot* of electronics!

---
What you do here is pat yourself on the back a lot.


I post goofy ideas, and outright blunders, too. Circuits that work,
and circuits that don't.


"Loose lips sink ships" is back-patting in a far less honest way.


--

John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Sat, 25 Apr 2015 18:31:24 +1000, "David Eather"
wrote:

On Sat, 25 Apr 2015 12:46:57 +1000, John Larkin
wrote:

On Sat, 25 Apr 2015 11:17:52 +1000, "David Eather"
wrote:

On Fri, 24 Apr 2015 10:59:43 +1000, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts
wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat
more
than once - it not longer visits 0 - 65535 without gaps (it
outputs a
665536 which needs 17 bits) and will miss a 16 bit number every
cycle
after the first, OR if the 17-th bit is ignored it will produce an
excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We just
peek at 18 bits of each register whenever we want a random number. An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields


A paraphrase:
"anyone who believes a deterministic circuit can produce true randomness
is in a state of sin"

So, we have preceded from the philosophical to the theological.



No, from speculation to Shannon.

We have spent the last month or so doing amazing things around the
Sampling Theorem. My customers aren't going to believe some of the
things the Wayback Machine can do, and I'm trying to write some manual
content that will convince them that what we're claiming is possible.
Sadly, few engineers have heard of the Sampling Theorem and even fewer
understand it.

What did Shannon say about deterministic circuits and truly random
noise?

Good book: The Idea Factory by Jon Gertner, about the glory days of
Bell Labs. One cool point is that most people who did great work at
Bell had breakfast or lunch with Harry Nyquist.

There is another book called The Idea Factory, about being a student
at MIT.


--

John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On 4/23/2015 8:06 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:35:38 -0400, rickman
wrote:

On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman
wrote:

On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman
wrote:

On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman
wrote:

On 4/16/2015 4:46 PM, John Fields wrote:

If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields


I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.

---
What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.

Can you post a contradictory example culled from the "larger field
of contenders" ?

I don't see where you have provided any examples to contradict.

---
I already posted a link to an 8 bit PRSG with 256 output states.

Did you miss it?

Apparently.

---
Well, then, for your perusal, here ya go:

https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0

This is hardly a "huge" counter...

---
Indeed, but the point made was to illustrate that NORing the outputs
of all of the stages preceding the rightmost and using that feedback
to force the PRSG into and out of the lockup state would cause it to
visit all of the 2^n possible states for that length of PRSG.

Uh, I had already indicated that this was possible and posted a link to
Peter Alfkie's app note about this for small LFSRs. So you are
restating my point.


Faulting the example because the counter isn't huge is disingenuous
since, if the lockup state is needed as part of the pattern, all
that's really needed to scale up to any PRSG length is a bunch of
diodes, a pullup resistor to Vcc, and an inverter on the outputs of
the diodes.

A bunch of diodes? I guess so, but the speed issue still remains. The
entire point of an LFSR is that the logic is small and simple with a
very short prop delay allowing fast speeds. Oring all the outputs of a
64 or 128 bit register is not so fast or simple even if done using state
of the techniques such as diode logic. lol

--

Rick

On 4/23/2015 8:44 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:42:23 -0400, rickman
wrote:

On 4/19/2015 3:15 AM, John Fields wrote:
On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

I'm not sure what you are going on about. Jasen's circuit does visit
every value from 0 to 65535 and does not visit 65536. In fact, if you
set it to 65536 it remains locked in that state. I think your analysis
is faulty... or mine is. I coded it up in a spread sheet and don't see
any problems with it.

---
Code is often beguiling, hardware is not.

For a 16 bit PRSG, setting it to 65536 is the same as setting it to
all zeroes, and unless there's feedback provided to lift it out of
lockup, that's where it'll stay.

You seem to have run off into the weeds on this one.

--

Rick

On Sat, 25 Apr 2015 15:49:06 -0400, rickman
wrote:

On 4/23/2015 8:06 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:35:38 -0400, rickman
wrote:

On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman
wrote:

On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman
wrote:

On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman
wrote:

On 4/16/2015 4:46 PM, John Fields wrote:

If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields


I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.

---
What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.

Can you post a contradictory example culled from the "larger field
of contenders" ?

I don't see where you have provided any examples to contradict.

---
I already posted a link to an 8 bit PRSG with 256 output states.

Did you miss it?

Apparently.

---
Well, then, for your perusal, here ya go:

https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0

This is hardly a "huge" counter...

---
Indeed, but the point made was to illustrate that NORing the outputs
of all of the stages preceding the rightmost and using that feedback
to force the PRSG into and out of the lockup state would cause it to
visit all of the 2^n possible states for that length of PRSG.

Uh, I had already indicated that this was possible and posted a link to
Peter Alfkie's app note about this for small LFSRs. So you are
restating my point.

---
As I recall, the schematic your link pointed to was a little
confusing - to me, anyway - so I decided to post something better
organized in order to illustrate the concept more clearly, not to
mention a working simulation. Which, BTW, neither you nor Alfkie
presented.

In any case, just for your information, that circuit's been around
since at least the late '60s, when I first came across it being used
as a bias-free scrambler.
---




Faulting the example because the counter isn't huge is disingenuous
since, if the lockup state is needed as part of the pattern, all
that's really needed to scale up to any PRSG length is a bunch of
diodes, a pullup resistor to Vcc, and an inverter on the outputs of
the diodes.

A bunch of diodes? I guess so, but the speed issue still remains.

---
How so?

if the diodes are all commoned on one end and followed by an
inverter, then the worst case delay will be one gate plus one diode,
which should be less than the delay through a stage of shift and
then back to the input through an EXOR.
---

The entire point of an LFSR is that the logic is small and simple with a
very short prop delay allowing fast speeds.

---
That's a rather myopic viewpoint since the main use of an LFSR, I
believe, is to generate a pseudo-random sequence regardless of the
rate at which it's doing so.
---

Oring all the outputs of a 64 or 128 bit register is not so fast
or simple even if done using state of the techniques such as
diode logic. lol

---
"State of the techniques"???

LOL indeed, since you don't even know how to talk about what you
don't know enough to talk about and, instead, offer up snarkiness as
a substitute for smart.

John Fields

Professional balloon pricker

On Sat, 25 Apr 2015 15:49:45 -0400, rickman
wrote:

On 4/23/2015 8:44 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:42:23 -0400, rickman
wrote:

On 4/19/2015 3:15 AM, John Fields wrote:
On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

I'm not sure what you are going on about. Jasen's circuit does visit
every value from 0 to 65535 and does not visit 65536. In fact, if you
set it to 65536 it remains locked in that state. I think your analysis
is faulty... or mine is. I coded it up in a spread sheet and don't see
any problems with it.

---
Code is often beguiling, hardware is not.

For a 16 bit PRSG, setting it to 65536 is the same as setting it to
all zeroes, and unless there's feedback provided to lift it out of
lockup, that's where it'll stay.

You seem to have run off into the weeds on this one.

---
Perhaps, but first of all, there's this:

DECIMAL BINARY
-------+---------------------
65535 1111 1111 1111 1111

So it should be apparent that it's impossible to set, or count to
decimal 65536 using a 16 bit register.

One extra count, to 65536, will result in the counter overflowing,
the MSB dropping into the bit bucket, and the counter's output
looking like this:

DECIMAL BINARY
-------+---------------------
65536 0000 0000 0000 0000

Get it?

On Sun, 26 Apr 2015 00:56:40 +1000, John Larkin
wrote:

On Sat, 25 Apr 2015 18:31:24 +1000, "David Eather"
wrote:

On Sat, 25 Apr 2015 12:46:57 +1000, John Larkin
wrote:

On Sat, 25 Apr 2015 11:17:52 +1000, "David Eather"
wrote:

On Fri, 24 Apr 2015 10:59:43 +1000, John Fields
wrote:

On Thu, 23 Apr 2015 09:02:02 -0700, John Larkin
wrote:

On Sun, 19 Apr 2015 02:15:07 -0500, John Fields
wrote:

On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts

wrote:


I was wondering about that myself... I'll see if there's a
cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to
repeat
more
than once - it not longer visits 0 - 65535 without gaps (it
outputs a
665536 which needs 17 bits) and will miss a 16 bit number every
cycle
after the first, OR if the 17-th bit is ignored it will produce
an
excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact,
all
of its dflops are/can be cleared in order to initialize it.

John Fields

We are just finishing up a waveform generator box that includes two
programmable-bandwidth Gaussian analog noise generators. We used 47
and 49 bit maximal-length shift registers, clocked at 64 MHz. We
just
peek at 18 bits of each register whenever we want a random number.
An
asymmetry of one code out of 2^48 is not a big concern.

---
But, regardless of your machinations, it still isn't truly random,
is it?

John Fields


A paraphrase:
"anyone who believes a deterministic circuit can produce true
randomness
is in a state of sin"

So, we have preceded from the philosophical to the theological.



No, from speculation to Shannon.

We have spent the last month or so doing amazing things around the
Sampling Theorem. My customers aren't going to believe some of the
things the Wayback Machine can do, and I'm trying to write some manual
content that will convince them that what we're claiming is possible.
Sadly, few engineers have heard of the Sampling Theorem and even fewer
understand it.

What did Shannon say about deterministic circuits and truly random
noise?

The random noise (if significant in level/effect) would make the whole
non-deterministic and hence the output fit most/all criteria for random.

On Sat, 25 Apr 2015 07:46:41 -0700, John Larkin
wrote:

On Sat, 25 Apr 2015 04:11:40 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 17:27:26 -0700, John Larkin
wrote:

On Fri, 24 Apr 2015 19:17:18 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 13:26:08 -0700, John Larkin
wrote:

On Fri, 24 Apr 2015 15:06:28 -0500, John Fields
wrote:

On Fri, 24 Apr 2015 07:43:47 -0700, John Larkin
wrote:


You seem to have lots of time for philosophical nonsense.

---
So, in the light of that castigation, I'm wrong and your scheme
produces a truly random output?

I have no idea what you might mean by "truly random output", and I
doubt that you do either.

---
Well, of course you don't and, your perception of being at the very
pinnacle of the food chain makes everything you don't understand
unimportant.

Define "truly random output", and I'll tell you if my board meets your
standards.

---
They're not _my_ standards, John, we all live by them.


OK, you have no definition of "truly random."


Most of us understand the concept, and you could too if Google were
your friend.
---

That's a matter of definition and philosophy. And a waste of time.

---
But your silly ramblings aren't?
---

Kinda like, from your earlier expressed but incorrect point of view,
latching relays have infinite gain.

If you'd have been paying attention, you might have noticed that
this thread started with Jim Thompson asking for a simple 4 bit
pseudo-random sequence generator for generating/testing a 16 state
datacom constellation.

Several solutions were offered but, as expected, you contested none
of them, provided no help, and waited until nearly the end to use
this channel to hawk your wares.

I'm not hawking anything. I don't expect anyone here to buy my stuff.

---
And yet the touting goes on, unabated.

This is an electronics discussion group. We need things to discuss.
And I do a *lot* of electronics!

---
What you do here is pat yourself on the back a lot.


I post goofy ideas, and outright blunders, too. Circuits that work,
and circuits that don't.

---
And a lot of off-topic garbage that has no place in a technical
discussion group.
---

"Loose lips sink ships" is back-patting in a far less honest way.

---
Actually, since I'm not in bed with the government, I meant that the
ships which would sink if I bandied my secrets around would be my
own lowly flotilla.

But, as usual, it seems you have trouble deciphering metaphors.

On 25/04/15 16:56, John Larkin wrote:
[...]

We have spent the last month or so doing amazing things around the
Sampling Theorem. My customers aren't going to believe some of the
things the Wayback Machine can do, and I'm trying to write some manual
content that will convince them that what we're claiming is possible.
Sadly, few engineers have heard of the Sampling Theorem and even fewer
understand it.

What did Shannon say about deterministic circuits and truly random
noise?

Good book: The Idea Factory by Jon Gertner, about the glory days of
Bell Labs. One cool point is that most people who did great work at
Bell had breakfast or lunch with Harry Nyquist.

There is another book called The Idea Factory, about being a student
at MIT.



Did you know that Shannon and Nyquist were late to lunch? The basic
sampling theorem was already stated in much the same way 35 years
earlier by E.T. Whittaker. I found traces of older references, but
haven't been able to get my hands on any.

Jeroen Belleman

On 4/25/2015 5:23 PM, John Fields wrote:
On Sat, 25 Apr 2015 15:49:06 -0400, rickman
wrote:

On 4/23/2015 8:06 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:35:38 -0400, rickman
wrote:

On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman
wrote:

On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman
wrote:

On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman
wrote:

On 4/16/2015 4:46 PM, John Fields wrote:

If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields


I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.

---
What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.

Can you post a contradictory example culled from the "larger field
of contenders" ?

I don't see where you have provided any examples to contradict.

---
I already posted a link to an 8 bit PRSG with 256 output states.

Did you miss it?

Apparently.

---
Well, then, for your perusal, here ya go:

https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0

This is hardly a "huge" counter...

---
Indeed, but the point made was to illustrate that NORing the outputs
of all of the stages preceding the rightmost and using that feedback
to force the PRSG into and out of the lockup state would cause it to
visit all of the 2^n possible states for that length of PRSG.

Uh, I had already indicated that this was possible and posted a link to
Peter Alfkie's app note about this for small LFSRs. So you are
restating my point.

---
As I recall, the schematic your link pointed to was a little
confusing - to me, anyway - so I decided to post something better
organized in order to illustrate the concept more clearly, not to
mention a working simulation. Which, BTW, neither you nor Alfkie
presented.

In any case, just for your information, that circuit's been around
since at least the late '60s, when I first came across it being used
as a bias-free scrambler.
---




Faulting the example because the counter isn't huge is disingenuous
since, if the lockup state is needed as part of the pattern, all
that's really needed to scale up to any PRSG length is a bunch of
diodes, a pullup resistor to Vcc, and an inverter on the outputs of
the diodes.

A bunch of diodes? I guess so, but the speed issue still remains.

---
How so?

if the diodes are all commoned on one end and followed by an
inverter, then the worst case delay will be one gate plus one diode,
which should be less than the delay through a stage of shift and
then back to the input through an EXOR.

The speed of your breadboard circuit is not really relevant. The speed
of a VLSI ASIC or an FPGA is what 99.999% of people will care about.
There is a reason why DTL is no longer used. Besides, the circuit slows
down with every diode added.


The entire point of an LFSR is that the logic is small and simple with a
very short prop delay allowing fast speeds.

---
That's a rather myopic viewpoint since the main use of an LFSR, I
believe, is to generate a pseudo-random sequence regardless of the
rate at which it's doing so.

Really? There are many ways of generating PRS. There are trade-offs
with each one. If you don't need the speed or small size an LFSR has
disadvantages compared to many others.


Oring all the outputs of a 64 or 128 bit register is not so fast
or simple even if done using state of the techniques such as
diode logic. lol

---
"State of the techniques"???

LOL indeed, since you don't even know how to talk about what you
don't know enough to talk about and, instead, offer up snarkiness as
a substitute for smart.

Lol. Yes, a typo makes for snarkiness. How about *state of the art*
techniques..? Yes, I was being sarcastic to illustrate the silliness of
mentioning DTL in a discussion of speed in LFSRs.

Are we done?

--

Rick

On 4/25/2015 6:03 PM, John Fields wrote:
On Sat, 25 Apr 2015 15:49:45 -0400, rickman
wrote:

On 4/23/2015 8:44 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:42:23 -0400, rickman
wrote:

On 4/19/2015 3:15 AM, John Fields wrote:
On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

I'm not sure what you are going on about. Jasen's circuit does visit
every value from 0 to 65535 and does not visit 65536. In fact, if you
set it to 65536 it remains locked in that state. I think your analysis
is faulty... or mine is. I coded it up in a spread sheet and don't see
any problems with it.

---
Code is often beguiling, hardware is not.

For a 16 bit PRSG, setting it to 65536 is the same as setting it to
all zeroes, and unless there's feedback provided to lift it out of
lockup, that's where it'll stay.

You seem to have run off into the weeds on this one.

---
Perhaps, but first of all, there's this:

DECIMAL BINARY
-------+---------------------
65535 1111 1111 1111 1111

So it should be apparent that it's impossible to set, or count to
decimal 65536 using a 16 bit register.

One extra count, to 65536, will result in the counter overflowing,
the MSB dropping into the bit bucket, and the counter's output
looking like this:

DECIMAL BINARY
-------+---------------------
65536 0000 0000 0000 0000

Get it?

Like I said, off in the weeds.

--

Rick

On Sun, 26 Apr 2015 09:32:00 -0400, rickman wrote:

On 4/25/2015 5:23 PM, John Fields wrote:
On Sat, 25 Apr 2015 15:49:06 -0400, rickman
wrote:

On 4/23/2015 8:06 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:35:38 -0400, rickman
wrote:

On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman
wrote:

On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman
wrote:

On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman
wrote:

On 4/16/2015 4:46 PM, John Fields wrote:

If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields


I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.

---
What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.

Can you post a contradictory example culled from the "larger field
of contenders" ?

I don't see where you have provided any examples to contradict.

---
I already posted a link to an 8 bit PRSG with 256 output states.

Did you miss it?

Apparently.

---
Well, then, for your perusal, here ya go:

https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0

This is hardly a "huge" counter...

---
Indeed, but the point made was to illustrate that NORing the outputs
of all of the stages preceding the rightmost and using that feedback
to force the PRSG into and out of the lockup state would cause it to
visit all of the 2^n possible states for that length of PRSG.

Uh, I had already indicated that this was possible and posted a link to
Peter Alfkie's app note about this for small LFSRs. So you are
restating my point.

---
As I recall, the schematic your link pointed to was a little
confusing - to me, anyway - so I decided to post something better
organized in order to illustrate the concept more clearly, not to
mention a working simulation. Which, BTW, neither you nor Alfkie
presented.

In any case, just for your information, that circuit's been around
since at least the late '60s, when I first came across it being used
as a bias-free scrambler.
---




Faulting the example because the counter isn't huge is disingenuous
since, if the lockup state is needed as part of the pattern, all
that's really needed to scale up to any PRSG length is a bunch of
diodes, a pullup resistor to Vcc, and an inverter on the outputs of
the diodes.

A bunch of diodes? I guess so, but the speed issue still remains.

---
How so?

if the diodes are all commoned on one end and followed by an
inverter, then the worst case delay will be one gate plus one diode,
which should be less than the delay through a stage of shift and
then back to the input through an EXOR.

The speed of your breadboard circuit is not really relevant. The speed
of a VLSI ASIC or an FPGA is what 99.999% of people will care about.
There is a reason why DTL is no longer used. Besides, the circuit slows
down with every diode added.

Shottky TTL is really DTL under the covers. D's aren't used much for
logic because (bipolar) Ts aren't either but DTL certainly isn't dead.


The entire point of an LFSR is that the logic is small and simple with a
very short prop delay allowing fast speeds.

---
That's a rather myopic viewpoint since the main use of an LFSR, I
believe, is to generate a pseudo-random sequence regardless of the
rate at which it's doing so.

Really? There are many ways of generating PRS. There are trade-offs
with each one. If you don't need the speed or small size an LFSR has
disadvantages compared to many others.


Oring all the outputs of a 64 or 128 bit register is not so fast
or simple even if done using state of the techniques such as
diode logic. lol

---
"State of the techniques"???

LOL indeed, since you don't even know how to talk about what you
don't know enough to talk about and, instead, offer up snarkiness as
a substitute for smart.

Lol. Yes, a typo makes for snarkiness. How about *state of the art*
techniques..? Yes, I was being sarcastic to illustrate the silliness of
mentioning DTL in a discussion of speed in LFSRs.

Are we done?

On Sun, 26 Apr 2015 09:32:00 -0400, rickman
wrote:

On 4/25/2015 5:23 PM, John Fields wrote:
On Sat, 25 Apr 2015 15:49:06 -0400, rickman
wrote:

On 4/23/2015 8:06 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:35:38 -0400, rickman
wrote:

On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman
wrote:

On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman
wrote:

On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman
wrote:

On 4/16/2015 4:46 PM, John Fields wrote:

If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields


I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.

---
What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.

Can you post a contradictory example culled from the "larger field
of contenders" ?

I don't see where you have provided any examples to contradict.

---
I already posted a link to an 8 bit PRSG with 256 output states.

Did you miss it?

Apparently.

---
Well, then, for your perusal, here ya go:

https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0

This is hardly a "huge" counter...

---
Indeed, but the point made was to illustrate that NORing the outputs
of all of the stages preceding the rightmost and using that feedback
to force the PRSG into and out of the lockup state would cause it to
visit all of the 2^n possible states for that length of PRSG.

Uh, I had already indicated that this was possible and posted a link to
Peter Alfkie's app note about this for small LFSRs. So you are
restating my point.

---
As I recall, the schematic your link pointed to was a little
confusing - to me, anyway - so I decided to post something better
organized in order to illustrate the concept more clearly, not to
mention a working simulation. Which, BTW, neither you nor Alfkie
presented.

In any case, just for your information, that circuit's been around
since at least the late '60s, when I first came across it being used
as a bias-free scrambler.
---




Faulting the example because the counter isn't huge is disingenuous
since, if the lockup state is needed as part of the pattern, all
that's really needed to scale up to any PRSG length is a bunch of
diodes, a pullup resistor to Vcc, and an inverter on the outputs of
the diodes.

A bunch of diodes? I guess so, but the speed issue still remains.

---
How so?

if the diodes are all commoned on one end and followed by an
inverter, then the worst case delay will be one gate plus one diode,
which should be less than the delay through a stage of shift and
then back to the input through an EXOR.

The speed of your breadboard circuit is not really relevant. The speed
of a VLSI ASIC or an FPGA is what 99.999% of people will care about.
There is a reason why DTL is no longer used. Besides, the circuit slows
down with every diode added.

---
If you go back to the beginning, you'll see that my offering was in
reference to Jim's request for a circuit which was to be simulated
in 74XX, so that's what he got.

I think you're wrong about the circuit slowing down since all the
shifters are being parallel clocked, making the delays per stage
equal except for skew.

Simulate it for yourself, it's easy enough to do. all you have to do
is edit the sim I posted by replacing the Ors with diodes and a
pullup, and run it.
---


The entire point of an LFSR is that the logic is small and simple with a
very short prop delay allowing fast speeds.

---
That's a rather myopic viewpoint since the main use of an LFSR, I
believe, is to generate a pseudo-random sequence regardless of the
rate at which it's doing so.

Really? There are many ways of generating PRS. There are trade-offs
with each one. If you don't need the speed or small size an LFSR has
disadvantages compared to many others.

---
Like?
---

Oring all the outputs of a 64 or 128 bit register is not so fast
or simple even if done using state of the techniques such as
diode logic. lol

---
"State of the techniques"???

LOL indeed, since you don't even know how to talk about what you
don't know enough to talk about and, instead, offer up snarkiness as
a substitute for smart.

Lol. Yes, a typo makes for snarkiness. How about *state of the art*
techniques..? Yes, I was being sarcastic to illustrate the silliness of
mentioning DTL in a discussion of speed in LFSRs.

Are we done?

---
No.

There's still the issue of why you think delays are additive through
AND ed diodes, and why you think it's silly to use diode steering
when it's appropriate.

John Fields

On Sun, 26 Apr 2015 09:32:28 -0400, rickman
wrote:

On 4/25/2015 6:03 PM, John Fields wrote:
On Sat, 25 Apr 2015 15:49:45 -0400, rickman
wrote:

On 4/23/2015 8:44 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:42:23 -0400, rickman
wrote:

On 4/19/2015 3:15 AM, John Fields wrote:
On 19 Apr 2015 03:14:30 GMT, Jasen Betts wrote:

On 2015-04-18, David Eather wrote:
On Thu, 02 Apr 2015 20:42:50 +1000, Jasen Betts wrote:


I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.


That is an absolute turd. It screws up if the cycle tries to repeat more
than once - it not longer visits 0 - 65535 without gaps (it outputs a
665536 which needs 17 bits) and will miss a 16 bit number every cycle
after the first, OR if the 17-th bit is ignored it will produce an excess
number of zeros.

No, that is absolute bull****.

it's this:
http://en.wikipedia.org/wiki/Lehmer_...mber_generator

except offset by -1 so that the Lehmer zero state (which is
disallowed) is excluded and the maximal state fits in 16 bits.

---
If the all-zeroes state is disallowed, then there'll always be a
bias on the output.

The circuit I posted includes the all-zeroes state and, in fact, all
of its dflops are/can be cleared in order to initialize it.

I'm not sure what you are going on about. Jasen's circuit does visit
every value from 0 to 65535 and does not visit 65536. In fact, if you
set it to 65536 it remains locked in that state. I think your analysis
is faulty... or mine is. I coded it up in a spread sheet and don't see
any problems with it.

---
Code is often beguiling, hardware is not.

For a 16 bit PRSG, setting it to 65536 is the same as setting it to
all zeroes, and unless there's feedback provided to lift it out of
lockup, that's where it'll stay.

You seem to have run off into the weeds on this one.

---
Perhaps, but first of all, there's this:

DECIMAL BINARY
-------+---------------------
65535 1111 1111 1111 1111

So it should be apparent that it's impossible to set, or count to
decimal 65536 using a 16 bit register.

One extra count, to 65536, will result in the counter overflowing,
the MSB dropping into the bit bucket, and the counter's output
looking like this:

DECIMAL BINARY
-------+---------------------
65536 0000 0000 0000 0000

Get it?

Like I said, off in the weeds.

---
Nice dodge.

John Fields

On Sun, 26 Apr 2015 12:58:31 -0400, krw wrote:

On Sun, 26 Apr 2015 09:32:00 -0400, rickman wrote:

On 4/25/2015 5:23 PM, John Fields wrote:

if the diodes are all commoned on one end and followed by an
inverter, then the worst case delay will be one gate plus one diode,
which should be less than the delay through a stage of shift and
then back to the input through an EXOR.

The speed of your breadboard circuit is not really relevant. The speed
of a VLSI ASIC or an FPGA is what 99.999% of people will care about.
There is a reason why DTL is no longer used. Besides, the circuit slows
down with every diode added.

Shottky TTL is really DTL under the covers. D's aren't used much for
logic because (bipolar) Ts aren't either but DTL certainly isn't dead.

---
Nice.

John Fields